• Preface @15
  • CHAPTER 1: Introduction @21
    • 1.1 Nanometer Designs @21
    • 1.2 What is Static Timing Analysis @22
    • 1.3 Why Static Timing Analysis? @24
      • Crosstalk and Noise @24
    • 1.4Design Flow @25
      • 1.4.1 CMOS Digital Designs @25
      • 1.4.2 FPGA Designs @28
      • 1.4.3 Asynchronous Designs @28
    • 1.5 STA at Different Design Phases @29
    • 1.6 Limitations of Static Timing Analysis @29
    • 1.7 Power Considerations @32
    • 1.8 Reliability Considerations @33
    • 1.9 Outline of the Book @33
  • CHAPTER 2: STA Concepts @35
    • 2.1 CMOS Logic Design @35
      • 2.1.1 Basic MOS Structure @35
      • 2.1.2 CMOS Logic Gate @36
      • 2.1.3 Standard Cells @38
    • 2.2 Modeling of CMOS Cells @40
    • 2.3 Switching Waveform @43
    • 2.4 Propagation Delay @45
    • 2.5 Slew of a Waveform @48
    • 2.6 Skew between Signals @50
    • 2.7 Timing Arcs and Unateness @53
    • 2.8 Min and Max Timing Paths @54
    • 2.9 Clock Domains @56
    • 2.10 Operating Conditions @59
  • CHAPTER 3: Standard Cell Library @63
    • 3.1 Pin Capacitance @64
    • 3.2 Timing Modeling @64
      • 3.2.1 Linear Timing Model @66
      • 3.2.2 Non-Linear Delay Model @67
        • Example of Non-Linear Delay Model Lookup @72
      • 3.2.3 Threshold Specifications and Slew Derating @73
    • 3.3 Timing Models - Combinational Cells @76
      • 3.3.1 Delay and Slew Models @77
        • Positive or Negative Unate @78
      • 3.3.2 General Combinational Block @79
    • 3.4 Timing Models - Sequential Cells @80
      • 3.4.1 Synchronous Checks: Setup and Hold @82
        • Example of Setup and Hold Checks @82
        • Negative Values in Setup and Hold Checks @84
      • 3.4.2 Asynchronous Checks @86
        • Recovery and Removal Checks @86
        • Pulse Width Checks @86
        • Example of Recovery, Removal and Pulse Width Checks @87
      • 3.4.3 Propagation Delay @88
    • 3.5 State-Dependent Models @90
      • XOR, XNOR and Sequential Cells @90
    • 3.6 Interface Timing Model for a Black Box @93
    • 3.7 Advanced Timing Modeling @95
      • 3.7.1 Receiver Pin Capacitance @96
        • Specifying Capacitance at the Pin Level @97
        • Specifying Capacitance at the Timing Arc Level @97
      • 3.7.2 Output Current @99
      • 3.7.3 Models for Crosstalk Noise Analysis @100
        • DC Current @102
        • Output Voltage @103
        • Propagated Noise @103
        • Noise Models for Two-Stage Cells @104
        • Noise Models for Multi-stage and Sequential Cells @105
      • 3.7.4 Other Noise Models @107
    • 3.8 Power Dissipation Modeling @108
      • 3.8.1 Active Power @108
        • Double Counting Clock Pin Power? @112
      • 3.8.2 Leakage Power @112
    • 3.9 Other Attributes in Cell Library @114
      • Area Specification @114
      • Function Specification @115
      • SDF Condition @115
    • 3.10 Characterization and Operating Conditions @116
      • What is the Process Variable? @116
      • 3.10.1 Derating using K-factors @117
      • 3.10.2 Library Units @119
  • CHAPTER 4: Interconnect Parasitics @121
    • 4.1 RLC for Interconnect @122
      • T-model @123
      • Pi-model @124
    • 4.2 Wireload Models @125
      • 4.2.1 Interconnect Trees @128
      • 4.2.2 Specifying Wireload Models @130
    • 4.3 Representation of Extracted Parasitics @133
      • 4.3.1 Detailed Standard Parasitic Format @133
      • 4.3.2 Reduced Standard Parasitic Format @135
      • 4.3.3 Standard Parasitic Exchange Format @137
    • 4.4 Representing Coupling Capacitances @138
    • 4.5 Hierarchical Methodology @139
      • Block Replicated in Layout @140
    • 4.6 Reducing Parasitics for Critical Nets @140
      • Reducing Interconnect Resistance @140
      • Increasing Wire Spacing @141
      • Parasitics for Correlated Nets @141
  • CHAPTER 5: Delay Calculation @142
    • 5.1 Overview @142
      • 5.1.1 Delay Calculation Basics @142
      • 5.1.2 Delay Calculation with Interconnect @144
        • Pre-layout Timing @144
        • Post-layout Timing @145
    • 5.2 Cell Delay using Effective Capacitance @145
    • 5.3 Interconnect Delay @150
      • Elmore Delay @151
      • Higher Order Interconnect Delay Estimation @153
      • Full Chip Delay Calculation @154
    • 5.4 Slew Merging @154
    • 5.5 Different Slew Thresholds @156
    • 5.6 Different Voltage Domains @159
    • 5.7 Path Delay Calculation @159
      • 5.7.1 Combinational Path Delay @160
      • 5.7.2 Path to a Flip-flop @162
        • Input to Flip-flop Path @162
        • Flip-flop to Flip-flop Path @163
      • 5.7.3 Multiple Paths @164
    • 5.8 Slack Calculation @165
  • CHAPTER 6: Crosstalk and Noise @166
    • 6.1 Overview @167
    • 6.2 Crosstalk Glitch Analysis @169
      • 6.2.1 Basics 169
      • 6.2.2 Types of Glitches @171
        • Rise and Fall Glitches @171
        • Overshoot and Undershoot Glitches @171
      • 6.2.3 Glitch Thresholds and Propagation @172
        • DC Thresholds @172
        • AC Thresholds @175
      • 6.2.4 Noise Accumulation with Multiple Aggressors @179
      • 6.2.5 Aggressor Timing Correlation @179
      • 6.2.6 Aggressor Functional Correlation @181
    • 6.3 Crosstalk Delay Analysis @183
      • 6.3.1 Basics @183
      • 6.3.2 Positive and Negative Crosstalk @186
      • 6.3.3 Accumulation with Multiple Aggressors @188
      • 6.3.4 Aggressor Victim Timing Correlation @188
      • 6.3.5 Aggressor Victim Functional Correlation @190
    • 6.4 Timing Verification Using Crosstalk Delay @190
      • 6.4.1 Setup Analysis @191
      • 6.4.2 Hold Analysis @192
    • 6.5 Computational Complexity @194
      • Hierarchical Design and Analysis @194
      • Filtering of Coupling Capacitances @194
    • 6.6 Noise Avoidance Techniques @195
  • CHAPTER 7: Configuring the STA Environment @197 7.1 7.2 7.3 What is the STA Environment? 180 Specifying Clocks 181 7.2.1 Clock Uncertainty 186 7.2.2 Clock Latency 188 Generated Clocks 190 Example of Master Clock at Clock Gating Cell Output, 194 Generated Clock using Edge and Edge_shift Options, 195 Generated Clock using Invert Option, 198 Clock Latency for Generated Clocks, 200 Typical Clock Generation Scenario, 200 7.4 7.5 Constraining Input Paths 201 Constraining Output Paths 205 Example A, 205 Example B, 206 Example C, 206 7.6 7.7 7.8 Timing Path Groups 207 Modeling of External Attributes 210 7.7.1 Modeling Drive Strengths 211 7.7.2 Modeling Capacitive Load214 Design Rule Checks 215 ixCONTENTS 7.9 7.10 7.11 7.12 Virtual Clocks 217 Refining the Timing Analysis219 7.10.1 Specifying Inactive Signals 220 7.10.2 Breaking Timing Arcs in Cells 221 Point-to-Point Specification 222 Path Segmentation 224 C HAPTER 8: Timing Verification 227 8.1 Setup Timing Check 228 8.1.1 Flip-flop to Flip-flop Path 231 8.1.2 Input to Flip-flop Path 237 Input Path with Actual Clock, 240 8.2 8.1.3 Flip-flop to Output Path242 8.1.4 Input to Output Path244 8.1.5 Frequency Histogram246 Hold Timing Check 248 8.2.1 Flip-flop to Flip-flop Path 252 Hold Slack Calculation, 253 8.2.2 8.2.3 Input to Flip-flop Path 254 Flip-flop to Output Path256 Flip-flop to Output Path with Actual Clock, 257 8.3 8.2.4 Input to Output Path259 Multicycle Paths 260 Crossing Clock Domains, 266 8.4 8.5 8.6 8.7 8.8 8.9 False Paths 272 Half-Cycle Paths 274 Removal Timing Check 277 Recovery Timing Check 279 Timing across Clock Domains 281 8.8.1 Slow to Fast Clock Domains 281 8.8.2 Fast to Slow Clock Domains 289 Examples295 Half-cycle Path - Case 1, 296 Half-cycle Path - Case 2, 298 Fast to Slow Clock Domain, 301 Slow to Fast Clock Domain, 303 xCONTENTS 8.10 Multiple Clocks305 8.10.1 Integer Multiples 305 8.10.2 Non-Integer Multiples 308 8.10.3 Phase Shifted 314 C HAPTER 9: Interface Analysis 317 9.1 IO Interfaces 317 9.1.1 Input Interface 318 Waveform Specification at Inputs, 318 Path Delay Specification to Inputs, 321 9.1.2 Output Interface 323 Output Waveform Specification, 323 External Path Delays for Output, 327 9.2 9.3 9.1.3 Output Change within Window 328 SRAM Interface 336 DDR SDRAM Interface 341 9.3.1 Read Cycle 343 9.3.2 Write Cycle 348 Case 1: Internal 2x Clock, 349 Case 2: Internal 1x Clock, 354 9.4 Interface to a Video DAC 360 C HAPTER 10: Robust Verification 365 10.1 On-Chip Variations 365 Analysis with OCV at Worst PVT Condition, 371 OCV for Hold Checks, 373 10.2 Time Borrowing 377 Example with No Time Borrowed, 379 Example with Time Borrowed, 382 Example with Timing Violation, 384 10.3 10.4 10.5 Data to Data Checks 385 Non-Sequential Checks392 Clock Gating Checks394 Active-High Clock Gating, 396 Active-Low Clock Gating, 403 Clock Gating with a Multiplexer, 406 xiCONTENTS Clock Gating with Clock Inversion, 409 10.6 Power Management 412 10.6.1 Clock Gating 413 10.6.2 Power Gating 414 10.6.3 Multi Vt Cells 416 High Performance Block with High Activity, 416 High Performance Block with Low Activity, 417 10.7 10.8 10.6.4 Well Bias 417 Backannotation 418 10.7.1 SPEF 418 10.7.2 SDF 418 Sign-off Methodology418 Parasitic Interconnect Corners, 419 Operating Modes, 420 PVT Corners, 420 Multi-Mode Multi-Corner Analysis, 421 10.9 Statistical Static Timing Analysis422 10.9.1 Process and Interconnect Variations 423 Global Process Variations, 423 Local Process Variations, 424 Interconnect Variations, 426 10.9.2 Statistical Analysis427 What is SSTA?, 427 Statistical Timing Libraries, 429 Statistical Interconnect Variations, 430 SSTA Results, 431 10.10 Paths Failing Timing?433 No Path Found, 434 Clock Crossing Domain, 434 Inverted Generated Clocks, 435 Missing Virtual Clock Latency, 439 Large I/O Delays, 440 Incorrect I/O Buffer Delay, 441 Incorrect Latency Numbers, 442 Half-cycle Path, 442 Large Delays and Transition Times, 443 Missing Multicycle Hold, 443 Path Not Optimized, 443 xiiCONTENTS Path Still Not Meeting Timing, 443 What if Timing Still Cannot be Met, 444 10.11 Validating Timing Constraints 444 Checking Path Exceptions, 444 Checking Clock Domain Crossing, 445 Validating IO and Clock Constraints, 446 A PPENDIX A: SDC 447 A.1 A.2 A.3 A.4 A.5 Basic Commands448 Object Access Commands449 Timing Constraints 453 Environment Commands461 Multi-Voltage Commands466 A PPENDIX B: Standard Delay Format (SDF) 467 B.1 B.2 What is it? 468 The Format 471 Delays, 480 Timing Checks, 482 Labels, 485 Timing Environment, 485 B.2.1 Examples 485 Full-adder, 485 Decade Counter, 490 B.3 B.4 The Annotation Process 495 B.3.1 Verilog HDL 496 B.3.2 VHDL499 Mapping Examples 501 Propagation Delay, 502 Input Setup Time, 507 Input Hold Time, 509 Input Setup and Hold Time, 510 Input Recovery Time, 511 Input Removal Time, 512 Period, 513 Pulse Width, 514 Input Skew Time, 515 xiiiCONTENTS No-change Setup Time, 516 No-change Hold Time, 516 Port Delay, 517 Net Delay, 518 Interconnect Path Delay, 518 Device Delay, 519 B.5 Complete Syntax 519 A PPENDIX C: Standard Parasitic Extraction Format (SPEF) 531 C.1 C.2 C.3 Basics 531 Format 534 Complete Syntax 550 Bibliography 561 Index .