2021.12.3

https://iverilog.fandom.com/wiki/Introduction

Design Process in General

  • design -> [simulate]
  • design -> netlist [synthesize]
  • netlist -> VLSI/FPGA layout [physical implementation tool]

FPGA physical implementation tool:

  • FPGA floor planner's process:
    • place
    • route

Verilog in Design Process

  • device under test
  • test bench: 不用考虑是否能综合

Icarus Verilog主要用于simulation