QnA

[TODO] Latch vs Register

[TODO] <= ?

Q:

reg <=生成Register？ wire <=生成Latch？

所以Verilog语法上<=在干嘛？ 单纯只是操作符重载吗？还是表示和时钟相关的操作？

A:

verilog-std-1364-2005.pdf: p118: 9.2.1:

The = assignment operator used by blocking procedural assignments is also used by procedural continuous␍ assignments and continuous assignments.

[TODO] synthesizable?

latch?