Cambrige Advanced Topics in Computer Architecture Reading List
Note: All Week 1 papers are not for assessment. You should not submit an essay on the topic of these papers.
Week 1: Trends in Computer Architecture
- Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures Agarwal, Hrishikesh, Keckler and Burger, ISCA, June 2000. [ IEEE Xplore ]
- *Dark Silicon and the End of Multicore Scaling *Esmaeilzadeh et al, IEEE Micro, 32:2, May-June 2012. [ IEEE Xplore ]
- *The Accelerator Wall: Limits to Chip Specialization *Fuchs and Wentzlaff, HPCA 2019. [ IEEE Xplore ]
Other optional material for week 1
- *A New Golden Age for Computer Architecture *Hennessy and Patterson, Communications of the ACM, Feb. 2019, 62(2), pp. 48-60 (Turing Lecture)
Week 2: State-of-the-art Processor Design
- BROOM: An Open-Source Out-of-Order Processor With Resilient Low-Voltage Operation in 28nm CMOS Celio, Chiu, Asanovic, Nikolic and Patterson. Hot Chips 30, 2019. [IEEE Xplore ]
- Inside 6th-Generation Intel Core: New Microarchitecture Code-Named Skylake Doweck et al, IEEE Micro, vol. 37, 2017 [IEEE Xplore ]
- The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips Davidson et al. IEEE Micro, 38(2), March-April, 2019 [IEEE Xplore ]
Other optional material for week 2
- Samsung M3 Processor Rupley, Burgess, Grayson, Zuraski, IEEE Micro, 39(2), March-April, 2019 [IEEE Xplore ]
Week 3: Memory system design
- Linearizing Irregular Memory Accesses for Improved Correlated Prefetching Jain and Lin, MICRO 2013 [ACM Digital Library]
- Best-Offset Hardware Prefetching Michaud, HPCA 2016 [IEEE Xplore] [Version with figure 6 fixed]
- Minnow: Lightweight Offload Engines for Worklist Management and Worklist-Directed Prefetching Zhang, Ma, Thomson and Chiou, ASPLOS 2018 [ACM Digital Library]
Other optional material for week 3
- Continuous Runahead: Transparent Hardware Acceleration for Memory Intensive Workloads Hashemi, Mutlu and Patt, MICRO 2016 [ACM Digital Library]
- Meet the Walkers: Accelerating Index Traversals for In-Memory Databases Kocberber, Grot, Picorel, Falsafi, Lim and Ranganathan [ACM Digital Library]
Week 4: Specification, verification and test
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ISA specification & verification:
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- Mandatory: Who Guards the Guards? Formal validation of the Arm v8-m architecture specification, OOPSLA 2017 [ACM Digital Library]
- ISA Semantics for ARMv8-A, RISC-V, and CHERI-MIPS, POPL 2019 [Open Access]
- Sail RISC-V docs: [GitHub]
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Instruction test generation:
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- Mandatory: Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification, IBM Research, IEEE Design and Test 2004 [IEEExplore]
- Randomised testing of a microprocessor model using SMT-solver state generation, 2015 [Science Direct]
- RISC-V torture tests: [GitHub]
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Additional material:
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- RISC-V tests: [GitHub]
- RISC-V formal framework: [[Open Access Slides](https://github.com/SymbioticEDA/riscv-formal http://www.clifford.at/papers/2017/riscv-formal/slides.pdf)]
Week 5: Hardware security (I)
Week 6: Hardware security (II)
Week 7: Hardware reliability
- StageWeb: Interweaving Pipeline Stages into a Wearout and Variation Tolerant CMP Fabric Gupta, Ansari, Feng and Mahlke, DSN 2010 [IEEE Xplore]
- Reunion: Complexity-Effective Multicore Redundancy Smolens, Gold, Falsafi and Hoe, MICRO 2006 [ACM Digital Library]
- Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor LaFrieda, İpek, Martínez and Manohar, DSN 2007 [IEEE Xplore]
Other optional material for week 7
- Architectural Core Salvaging in a Multi-Core Processor for Hard-Error Tolerance Powell, Biswas, Gupta and Mukherjee, ISCA 2009 [ACM Digital Library]
- Relax: An Architectural Framework for Software Recovery of Hardware Faults De Kruijf, Nomura and Sankaralingam, ISCA 2010 [ACM Digital Library]