Issue, Execute and Writeback in Gem5

• Q: how next pc (predPC) is generated?

TODO:

StaticInst contains

advancePC(*next_pc)

X86StaticInst overrides advancePC from StaticInst.

X86ISA::X86StaticInst and X86ISA::X86MicroopBase override advancePC from StaticInst.

macroop pc

• src/cpu/o3/fetch.cc:

  Fetch::fetch(bool &status_change) {
    ...
    predictedBranch |= lookupAndUpdateNextPC(instruction, *next_pc);
    ...
  }
  

  • src/cpu/o3/fetch.cc:

    bool
    Fetch::lookupAndUpdateNextPC(const DynInstPtr &inst, PCStateBase &next_pc) {
      ...
      inst->staticInst->advancePC(next_pc);
      ...
    }
    

    • src/arch/x86/insts/static_inst.hh:

      advancePC(PCStateBase &pcState) const override {
          pcState.as<PCState>().advance();
      }
      

      • src/arch/x86/pcstate.hh:

        advance() override {
            Base::advance();
            _size = 0;
        }
        

        • src/arch/generic/pcstate.hh:

          advance() override {
              this->_pc = this->_npc;
              this->_npc += InstWidth;
          }
          

          The question becomes where and who calculates _npc?