Chapter 1. Introduction

• 🤔message-signaled interrupts (MSIs):
• 🤔traditional wired interrupts:

1.3.2 External interrupts with IMSICs

Fundamentally, a message-signaled interrupt is simply a memory write to a specific address that hardware accepts as indicating an interrupt. ... the receiving IMSIC interprets the write as an external interrupt for the respective hart.

TODO: MMU是否也要参与？

1.5 Selection of harts tp receive an interrupts

PLIC与APLIC的差异：

The original Platform-Level Interrupt Controller (PLIC) for RISC-V is configurable so each interrupt source signals external interrupts to any subset of the harts, potentially all harts. When multiple harts receive an external interrupt from a single cause at the PLIC, the first hart to claim the interrupt at the PLIC is the one responsible for servicing it. Usually this ...

For the reasons already given, the Advanced PLIC supports sending each signaled interrupt to only a single hart chosen by software, not to multiple harts.

对于一个中断： PLIC可通知多个hart，第一个claim的hart负责处理，因此可能会出现竞争； APLIC由软件选择一个hart负责处理。

Chapter 2. Control and Status Registers (CSRs) Added to Harts

2.5. Access control by the state-enable CSRs

这个是为了避免covert channel(存在安全问题），不是几分钟能看透的，先跳过了。

Chapter 3. Incoming MSI Controller (IMSIC)

3.9. Top external interrupt CSRs (mtopei, stopei, vstopei)

IMSIC和APLIC的差异：IMSIC的interrupt_identity==interrupt_priority， 而APLIC的可以不等。 IMSIC设计的理由见3.3. Interrupt priorities。

Chapter 4. Advanced Platform-Level Interrupt Controller (APLIC)

This chapter specifies an Advanced PLIC (APLIC) that is not backward compatible with the earlier RISC-V PLIC.

APLIC和PLIC的差异：APLIC不兼容PLIC

• 注1：有想要搞一个systemverilog写的APLIC的开源组件
• 注2：有Duo-PLIC的草案，但不一定能成标准
  • 详见：https://github.com/riscv/riscv-aia/blob/main/doc/src/DuoPLIC.tex

Full conformance to the Advanced Interrupt Architecture requires the APLIC. However,␍ a workable system can be built substituting the older PLIC instead, assuming only wired interrupts to␍ harts, not MSIs.

AIA的支持必须要有APLIC，可以没有MSI，但不一定能成标准

While not prohibited, this arrangement is likely to be less efficient than having all harts share a single APLIC.

为了性能，推荐全局一个APLIC。

Multiple APLICs are presumably more likely to arise when groups of devices are physically distant from one another, perhaps even on separate chips (including chiplets in a multi-chip module).

多APLICs用于物理上隔离的设备（chiplets）。

When harts have IMSICs to support MSIs, a system may easily contain multiple APLICs for converting wired interrupts into MSIs,

当IMSICs存在时，APLIC的角色变为wired interrupts转换为MSIs。