Yosys
https://yosyshq.readthedocs.io/projects/yosys/en/0.41/introduction.html
Levels of Abstraction
| Levels | Process | Yosys |
|---|---|---|
| System Level | ||
| System Design | ||
| High Level | ||
| High Level Synthesis (HLS) | ||
| Behavioral Level | ||
| Behavioral Synthesis | ✅ | |
| Register-Transfer Level (RTL) | ✅ | |
| RTL Synthesis | ✅ | |
| Logical Gate Level | ✅ | |
| Logic Synthesis | ✅ | |
| Physical Gate Level | ||
| Cell Library | ||
| Switch Level |
Adapted from [yosys's levels_of_abstraction.svg](https://yosyshq.readthedocs.io/projects/yosys/en/latest/_images/levels_of_abstraction.svg)